1. Technical Field
The present invention relates to a data processing system, and more particularly, to a method of interrupt processing within a data processing system.
2. Description of Related Art
Interrupt handling mechanisms have been developed for dealing more effectively with input/output transactions between a micro-processor and a peripheral device connected to the central processing unit. Basically, whenever the peripheral device requires central processing unit support as part of an input/output operation, it sends an interrupt signal to the processor to notify it that an interrupt condition exists at the peripheral device. Depending on the type of interrupt signal that is received, the processor may elect to either ignore the interrupt and finish what it is doing, or it can handle the interrupt when it receives it. Once the interrupt signal is handled by the interrupt handling mechanism, the processor returns to the state it was before the interrupt took place. An interrupt source may be a keyboard, an adapter card, or any other device connected to the processor.
The processing of an interrupt request typically involves the processor interrogating the source of the interrupt, performing specific functions based upon the type of the interrupt, or even resetting or turning off the interrupt request. There are several different types of interrupt requests. For example, when an interrupt request is deferred by the processor, it is said to be a masked request. An interrupt request may also be prioritized by a particular system if the request from one device is more urgent than the request from another device. Thus, the request from one device will have priority over the request of the other device. The priority of an interrupt request is predefined by the system. When an interrupt request has been accepted by the processor, a subsequent interrupt request cannot interrupt the current interrupt unless it has priority over the current interrupt. If it does not have priority, then the subsequent request must wait until the current request is handled.
As systems become more complex with more numerous peripheral devices, the numerous interrupt requests generated by these devices slows the processor down. Therefore, interrupt controllers were developed to delegate certain interrupt functions from the processor to the interrupt controller. Such interrupt controllers allow the processor to continue working without servicing an interrupt at the time that it is first made. The interrupt controller is used to monitor multiple interrupt sources while only interrupting the processor using a single interrupt line.
Such interrupt controllers were initially developed primarily for a single processor system which had few interrupt sources or priority levels. As technology developed, multiprocessor systems came into existence. Generally, in a multiprocessor system, more than one of the processors are capable of performing a particular interrupt request. However, in order to allow all of the processors that are capable of performing such a request to do so, an interrupt signal from each interrupt source would have to be wired to each processor or interrupt controller that is capable of servicing such an interrupt. This leads to increases in bus complexity because of the number of interrupt signals that have to be hard-wired to each processor.
To satisfy the needs of multi-processing data systems such as these, dedicated interrupt controllers were provided for each processor in the system. However, that approach was very costly and did not allow for effective management of the interrupts as the number of interrupts sources and priority levels increased. Scalable interrupt sub-systems were developed to solve such growing pains.
Arndt, et al. (U.S. Pat. No. 5,701,495) disclosed a scalable system interrupt structure for multi-processing systems and is hereby incorporated by reference. The interrupt sub-system provides for queuing of interrupts from many sources and presenting interrupts to the best processor in a multiprocessor system. This is accomplished by separating the internal interrupt mechanism into two layers: an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service or process the interrupt. By providing two layers within the interrupt sub-system, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software and provides hardware independent functionality. Interrupt lines from various interrupt sources are input into an interrupt source controller. The interrupt source controller is connected to a system interconnect fabric, such as a bus, which is also connected to the interrupt presentation controllers.
Interrupt presentation controllers are used to present interrupts to the system""s processors. Each processor has associated with it a memory mapped interrupt management area. Some implementations distribute the interrupt presentation layer by placing the interrupt management areas for some of the platform processors in one chip, and the interrupt management areas of the rest of the processors in other chips.
The reason for placing the interrupt management area on different chips is that as symmetrical multiprocessor computer systems grow larger, it is impractical to integrate the interrupt presentation controller for all of the system""s processors into a single chip. However, when the interrupt management areas are implemented on different chips, interrupt messages may have to be forwarded between implementing chips if no accepting processor can be found in the original presentation layer chip.
Furthermore, if priority-based assignment is implemented, then the priority of the least favorite processor may have to be broadcast to the other presentation layer chips.
Methods for allowing for the proper assignment of interrupt to multiple interrupt presentation controllers are currently very complex and/or require a significant amount of specialized signal wires between the multiple controllers. Hence, there is a need for a method of distribution of interrupts to multiple interrupt presentation controllers which is less complex and does not require a significant amount of specialized signal wires.
The present invention provides a simple method for distributing interrupts to multiple interrupt presentation controllers and avoids the use of a significant amount of signal lines previously required in multiprocessor systems. An input interrupt message from the interrupt source controller contains a service queue number, an interrupt priority, and an interrupt source number. This input interrupt message is input into an interrupt presentation controller and the following fields are added to the input interrupt message: interrupt presentation controller number, search priority, and best priority. Once this is done, the input interrupt message is passed between the interrupt presentation controllers in a sequential fashion such that the collection of controllers forms a logical ring.
A new interrupt message on its first circle of the ring discovers the priority of processors capable of handling the interrupt. The least favorite level that exists on each processor is retained in the best priority field of the input interrupt message. If a subsequent interrupt presentation controller has a less favored level than what has already been retained, then that value is placed in the best priority field. The input interrupt message then makes a second pass through the interrupt presentation controllers.
On the subsequent pass, the input interrupt message is assigned to the first processor that is both capable of taking the interrupt and also has an equal or lower priority to that noted on the first pass as the best priority.